Method of reducing junction spiking through a wall surface of an overetched contact via

ABSTRACT

The present invention pertains to a semiconductor device microstructure, and to a method of forming that microstructure, which reduces or prevents junction spiking and to a method of forming that microstructure. In particular, a semiconductor contact microstructure comprises a feature which includes a silicon base and at least one sidewall extending upward from the silicon base. The sidewall includes a silicon portion in contact with the silicon base, where the height of the silicon portion of the sidewall above the silicon base is typically less than about 0.5 μm. The sidewall also includes at least one portion which comprises a first dielectric material which is in contact with (and typically extends upward from) the silicon portion of the sidewall. Overlying at least the silicon portion of the sidewall is a layer of a second dielectric material, preferably silicon oxide. Typically, a diffusion barrier layer overlies the silicon base, the layer of second dielectric material, and at least part of the sidewall portion which is comprised of the first dielectric material. The method comprises the steps of: a) providing a semiconductor device feature which includes a silicon base and at least one sidewall extending upward from the silicon base, where the sidewall includes at least one silicon portion in contact with the silicon base, and another portion comprising a first dielectric material which is in contact with the silicon portion of the sidewall; and b) creating a layer of a second dielectric material, preferably silicon oxide, over the at least one silicon sidewall portion. The method may include additional steps: c) sputter etching to remove dielectric material from the surface of the silicon base; and d) applying a diffusion barrier material over the silicon base, the layer of second dielectric material, and at least a portion of the sidewall comprising the first dielectric material. Typically, both the first and second dielectric materials are silicon oxide.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention pertains to a structure and method forreducing or preventing junction spiking due to silicon diffusion througha wall surface of an overetched contact via formed in a siliconsubstrate.

[0003] 2. Brief Description of the Background Art

[0004] In the fabrication of multi-layered semiconductor devices, it iscommon to have a single-crystal silicon substrate with a dielectriclayer overlying the silicon substrate. Electrical contacts may be formedby creating an opening through the dielectric layer to the surface ofthe silicon substrate. The opening is subsequently filled with aconductive material, which is typically a metal such as aluminum orcopper.

[0005] One of the preferred methods of producing the opening (i.e.,contact via) through the dielectric layer to the surface of the siliconsubstrate is by plasma etching through a mask on the surface of thedielectric layer. Variance occurs in this etching process and somedegree of overetch into the silicon substrate is necessary to ensurethat the contact is completely open (i.e., there is no dielectricmaterial remaining between the metal contact and the silicon substrate).The degree of overetch will vary with overall pattern factors andgeometric considerations.

[0006] Conventional integrated circuit processing steps can causesilicon atoms to diffuse from single-crystal silicon into a contact ofpure aluminum or pure copper adjacent to the single-crystal silicon.When the diffusion is sufficient to short out a shallow p-n junction inthe silicon, this phenomenon is known as junction spiking.

[0007] In order to prevent such junction spiking, a diffusion barrierlayer is typically applied over the internal surface of the contact viaafter etching of the opening through the dielectric layer. One of thepreferred methods of application of the diffusion barrier layer is byphysical vapor deposition (PVD), in particular, high density plasmasputter deposition. The use of high density plasma sputtering techniquesresults in the deposition of diffusion barrier layers having excellentbarrier properties, even in difficult-to-fill small feature size contactvias. However, even when diffusion barrier layers are deposited usinghigh density plasma sputtering techniques, junction spiking of contactsis still occasionally observed.

[0008] Therefore, it would be desirable to provide a new devicemicrostructure and method of forming the structure which would reduce orprevent junction spiking due to silicon diffusion through a wall surfaceof an overetched contact via.

SUMMARY OF THE INVENTION

[0009] We have discovered a new semiconductor contact microstructure anda method of forming the structure prevents the which reduces junctionspiking in semiconductor contact vias. The structure is applicable whenthe contact via has a three-dimensional shape which makes it difficultto apply a diffusion barrier layer in the area adjacent the interfacebetween a silicon surface and a metal such as aluminum or copper.

[0010] In particular, the semiconductor contact microstructure comprisesa feature which includes a silicon base and at least one sidewallextending upward from the silicon base. The sidewall includes a siliconportion in contact with the silicon base. Typically the height of thesilicon portion of the sidewall above the silicon base is less thanabout 0.5 μm. The sidewall also includes at least one portion whichcomprises a first dielectric material which is in contact with (andtypically extends upward from) the silicon portion of the sidewall.Overlying at least the silicon portion of the sidewall is a layer of asecond dielectric material, preferably silicon oxide. In mostapplications, a diffusion barrier layer overlies the silicon base, thelayer of second dielectric material, and at least part of the sidewallportion which is comprised of the first dielectric material. Typically,the first and second dielectric materials are both silicon oxide,although the first dielectric material may be a low k dielectric, whilethe second dielectric material may be silicon oxide.

[0011] The method comprises the steps of: providing a semiconductordevice feature which includes a silicon base and at least one sidewallextending upward from the silicon base, where the sidewall includes atleast one silicon portion in contact with the silicon base, and anotherportion comprising a first dielectric material which is in contact withthe silicon portion of the sidewall; and, creating a layer of a seconddielectric material, preferably silicon oxide, over the at least onesilicon sidewall portion. The method may also include subsequent stepsof sputter etching to remove dielectric material from the surface of thesilicon base; and, applying a diffusion barrier material over thesilicon base, the layer of second dielectric material, and at least aportion of the sidewall comprising the first dielectric material.

[0012] The method of the invention is particularly effective when usedto prepare electrical contacts having a feature size of less than about0.5 μm and an aspect ratio of greater than about 2:1.

[0013] The method of the invention greatly reduces or eliminatesjunction spiking at the bottom of contact vias when the via has beenoveretched, leaving via sidewalls exposed at the bottom of the contactwhich comprise silicon. Application of a dielectric layer, such assilicon oxide, over the portion of the via wall surface which comprisessilicon, followed by removal of any excess dielectric formed upon thebottom surface of the via, and subsequent application of a diffusionbarrier layer over the interior of the via surface, reduces thepossibility of junction spiking after filling of the via with aconductive metal, such as aluminum or copper. The presence of thedielectric material on the silicon sidewall of the via is effective toprotect this portion of the sidewall from diffusion into the conductivemetal with subsequent current leakage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 shows a schematic representative of the appearance of atypical photomicrograph of small contacts 102 (approximately 0.25 μmfeature size) and larger contacts 104 (approximately 0.5 μm) which werefabricated simultaneously, so that the contact vias were etchedsimultaneously during the same etching process on the same siliconwafer.

[0015]FIG. 2 shows an overetched contact via 8.

[0016]FIG. 3 shows the contact via of FIG. 2 after deposition of adiffusion barrier layer 18 over the surface of the contact via 8 usinghigh density plasma deposition techniques.

[0017]FIG. 4 shows the contact via of FIG. 2 after formation of adielectric layer 16 on the bottom 6 and on the exposed silicon portion14 of the contact-via sidewalls 4.

[0018]FIG. 5 shows one semiconductor microstructure of the presentinvention, which is the contact via of FIG. 4 after sputter etching toremove the dielectric layer 16 from the bottom 6 of the contact via 8.

[0019]FIG. 6 shows a second semiconductor microstructure of the presentinvention, after deposition of a barrier layer 22 over themicrostructure shown in FIG. 6.

[0020]FIG. 7 shows a third semiconductor microstructure of the presentinvention, after deposition of a metal fill layer 24 to form a contact.

DETAILED DESCRIPTION OF THE INVENTION

[0021] We have discovered a new semiconductor contact microstructure anda method of forming the structure which reduces or eliminates junctionspiking in semiconductor contact vias. The structure is particularlyapplicable when the contact via has a three-dimensional shape whichmakes it difficult to apply a diffusion barrier layer in the areaadjacent the interface between a silicon surface and a metal such asaluminum or copper.

[0022]FIG. 1 shows a schematic which illustrates the appearance of atypical photomicrograph of small contacts (approximately 0.25 μm featuresize) and larger contacts (approximately 0.5 μm) which were fabricatedsimultaneously. This permitted a comparison of the junction spikingphenomenon as a function of the feature size. Referring to FIG. 1,reference numeral 102 designates small contacts having a feature size ofapproximately 0.25 μm, and reference numeral 104 designates largercontacts having a feature size of approximately 0.5 μm. The contacts 102and 104 exhibited the basic contact via structure shown in FIG. 2 anddescribed in detail below. A diffusion barrier layer oftitanium/titanium nitride about 200 Å to about 600 Å thick was appliedover the basic contact via using a high density plasma reactivesputtering technique, followed by an aluminum fill of the contact usinga high density plasma sputtering technique, which is described in moredetail subsequently herein. A fairly severe degree of junction spiking106 was observed with for this microstructure for larger contacts; nojunction spiking was observed with the smaller contacts.

[0023]FIG. 2 shows a typical contact via 8 etched through a dielectriclayer 10 and overetched into a silicon substrate 12. During etching ofcontact vias, some degree of overetch into the underlying siliconsubstrate 12 is necessary to ensure that the contacts are completelyopen. As shown in FIG. 2, overetching of contact vias exposes an etchedsilicon surface 15 on the lower sidewall 14, as well as the bottom 6, ofthe contact via 8.

[0024] With reference to FIG. 3, after etching of the opening throughthe dielectric layer 10, a diffusion barrier layer 18 is applied overthe internal surface of the contact via 8 to prevent the diffusion ofadjacent materials across the boundaries between the materials. When theconductive fill material 20 is aluminum, the diffusion barrier layer 18is typically a combination of a titanium wetting layer followed by atitanium nitride barrier layer. The diffusion barrier layer 18 may betungsten/tungsten nitride. When the conductive fill material 20 iscopper, the diffusion barrier layer 18 is typically a combination of atantalum wetting layer followed by a tantalum nitride barrier layer.

[0025] One of the preferred methods of application of the diffusionbarrier layer 18 is by physical vapor deposition (PVD), in particular,high density plasma sputtering. In particular, high density plasmasputtering refers to deposition sputtering, where sputtered material ispassed through an ionization means, such as an inductively coupled RFsource, to create a high density, inductively coupled RF plasma betweenthe sputtering cathode (target) and the substrate support electrode.This ensures that a higher portion of the sputtered emission is in theform of ions at the time it reaches the substrate surface. Although notalways required, depending on the device topography and the amount ofsubstrate self-bias, the substrate toward which the sputtered ions aremoving is typically biased to attract the incoming ions. The use of highdensity plasma sputtering techniques results in the deposition ofdiffusion barrier layers having excellent barrier properties, even indifficult-to-fill small feature size contacts.

[0026] However, high density plasma sputter deposition is not completelyconformal when the feature size of the contact is below about 0.25 μmand the aspect ratio of the via exceeds about 2:1. As a result, theamount of diffusion barrier layer deposited on the walls of the via nearthe bottom of the contact is minimal, even though the thickness of thediffusion barrier layer at the bottom of the contact (i.e., on thesilicon surface at the bottom of the contact) is more than adequate.

[0027] Despite the minimal thickness of the diffusion barrier layerdeposited near the bottom of the contact for high aspect ratio features,PVD is generally preferred over chemical vapor deposition (CVD), whichprovides a more conformal coating. This is because PVD is a cleaner,more environmentally friendly process; chemical vapor deposition (CVD)results in the production of undesirable chemical by-products.

[0028] The present invention permits the use of the cleaner PVD(sputtering) deposition of the diffusion barrier layer without theconcern that junction spiking may occur in comers at the base of thecontact, where the minimal thickness of a diffusion barrier layer mightpermit diffusion of silicon into an aluminum fill layer.

[0029]FIG. 3 shows a diffusion barrier layer 18 that has been depositedover the interior surface 2 of an overetched contact via 8 (such as thatshown in FIG. 2) using high density plasma deposition techniques. Highdensity plasma sputter deposition provides less barrier layer coverageon the sidewalls 4 than on the bottom 6 of a contact via 8, and minimalbarrier layer coverage of the lower sidewalls 14, which are exposedsilicon 12 due to overetching. Because the barrier layer 18 is so thin(as shown in the circled area indicated by reference numeral 17) on thelower sidewalls 14, it provides minimal protection against silicondiffusion. As such, although the contact bottom 6 is protected againstmigration of silicon 12 into the aluminum or copper fill layer 20, thesilicon may migrate through the thin diffusion barrier layer 18 on thelower sidewall 14 of an overetched contact 8.

[0030] It is much easier to apply a continuous diffusion barrier layerover the surface of a larger contact via having a lower aspect ratiothan it is to apply a continuous diffusion barrier layer over thesurface of a small contact via having a higher aspect ratio. One skilledin the art would then presume that junction spiking would occur lessfrequently with larger contacts. However, as shown in FIG. 1, weobserved significantly more junction spiking with larger contacts thanwith smaller contacts that had been formed in the same substrate duringthe same etching process.

[0031] With reference to FIG. 2, we determined that, because largercontact vias etch faster, the larger contact vias exhibited a muchgreater degree of overetch into the underlying silicon layer 12 than thesmaller contact vias. As a result, there is more exposed silicon surface15 on the lower sidewalls 14 of the larger contacts than on the lowersidewalls 14 of the smaller contacts. The increase in exposed siliconsurface 15 provides an increased area available for migration of thesilicon 12 into the aluminum or copper fill layer 20. Diffusion ofsilicon 12 into the aluminum or copper fill layer 20 creates a pathwayfor junction spiking, which increases current leakage.

[0032] The present invention pertains to a device microstructure whichreduces or prevents junction spiking and to a method of forming thatmicrostructure. In particular, applicants have discovered that a contactvia microstructure having an exposed silicon base and overetched siliconsidewalls adjacent the silicon base can be better protected frommigration of the silicon into a metallic fill of the contact byproviding a layer of a dielectric material such as silicon oxide overthe overetched silicon sidewalls prior to application of the diffusionbarrier layer and the metallic fill. The presence of the dielectricmaterial on the overetched silicon sidewalls reduces or preventsjunction spiking in a completed contact. Applicants have formed thecontact via microstructure described above by forming a layer of siliconoxide over the silicon surfaces exposed during etch of the basic contactvia, and then removing the portion of the silicon oxide layer whichoverlies the bottom of the contact via by sputter cleaning (etching)under anisotropic conditions, which leaves intact the silicon oxidelayer on the exposed silicon sidewalls, while removing the silicon oxideon the silicon surface at the bottom of the contact via. Subsequently, abarrier layer was applied over the interior of the contact via, followedby a metal fill of the contact. The contact via microstructure producedby this method is effective in reducing or preventing migration ofsilicon through the contact via sidewall to the metallic fill within thecontact via, which leads to subsequent current leakage.

[0033] I. Definitions

[0034] As a preface to the detailed description, it should be notedthat, as used in this specification and the appended claims, thesingular forms “a”, “an”, and “the” include plural referents, unless thecontext clearly dictates otherwise. Thus, for example, the term “asemiconductor” includes a variety of different materials which are knownto have the behavioral characteristics of a semiconductor, reference toa “plasma” includes a gas or gas reactants activated by an RF or DC (orboth) glow discharge, and reference to “the contact material” includesany conductive, metallic material which has a melting point temperaturewhich enables its use as a contact via fill material.

[0035] Specific terminology of particular importance to the descriptionof the present invention is defined below.

[0036] The term “aluminum” includes alloys of aluminum of the kindtypically used in the semiconductor industry. Such alloys includealuminum-copper alloys, and aluminum-copper-silicon alloys, for example.

[0037] The term “aspect ratio” refers to the ratio of the heightdimension to the width dimension of particular openings into which anelectrical contact is to be placed. For example, a contact via openingwhich typically extends in a tubular form through multiple layers has aheight and a diameter, and the aspect ratio would be the height of thetubular divided by the diameter. The aspect ratio of a trench would bethe height of the trench divided by the minimal travel width of thetrench at its base.

[0038] The term “bottom coverage” refers to the ratio of the thicknessof the film layer deposited at the bottom of an interconnect feature,such as a contact via, to the thickness of the film layer deposited onthe field surface, expressed as a percentage. For example, if the layerof film deposited at the bottom of a contact via has a thickness of 1μm, and the layer of film deposited on the field surface has a thicknessof 10 μm, the bottom coverage of the film would be 10%.

[0039] The term “completely filled” refers to the characteristic of afeature, such as a trench or via, which is filled with a conductivematerial, wherein there is essentially no void space present within theportion of the feature filled with conductive material.

[0040] The term “copper” includes alloys of copper of the kind typicallyused in the semiconductor industry.

[0041] The term “diffusion barrier layer” refers to any barrier film orcoating on the surface of a contact via or other feature which iseffective as a barrier to prevent diffusion of atoms of material fromone layer into atoms of another material in an adjacent layer.

[0042] The term “feature” refers to contacts, vias, trenches, and otherstructures which make up the topography of the substrate surface. Asused herein, the term “small feature” refers to a feature having a widthdimension (i.e., diameter) of less than 0.5 μm.

[0043] The term “high density plasma sputter deposition” or “ion metalplasma sputter deposition” refers to sputter deposition, preferablymagnetron sputter deposition (where a magnet array is placed behind thetarget), where a high density, inductively coupled RF plasma is createdbetween the sputtering cathode and the substrate support electrode,whereby at least a portion of the sputtered emission is in the form ofions at the time it reaches the substrate surface. In high densityplasma sputtering, the percentage of target material which remainsionized approaching the substrate surface ranges from 10% up to about90%.

[0044] The term “tantalum nitride” refers to a compound comprisingtantalum and nitrogen and having the general formula TaN_(x), wherein xranges from about 0.8 to about 1.5.

[0045] The term “titanium nitride” refers to a compound comprisingtitanium and nitrogen and having the general formula TiN_(x), wherein xranges from about 0.8 to about 1.5.

[0046] II. An Apparatus for Practicing the Invention

[0047] The method of the present invention may be carried out usingequipment/apparatus standard in the industry for semiconductorprocessing. Preferably the equipment enables the user to perform all ofthe process steps under a controlled environment so that the substrateis not exposed to contamination or undesirable chemical reactants. Themore preferred PVD apparatus enables separate control of power to theplasma source generator and power used to bias the semiconductorsubstrate. Another preferred feature of the PVD apparatus is an abilityto provide a high density plasma. If the dielectric layer to be formedover the silicon portion of the contact sidewall is to be formed byoxidation of the silicon surface to silicon oxide, the apparatusincludes rapid thermal processing capability. If this dielectric layeris deposited using CVD techniques, then an apparatus which enables CVDis required, for example. Removal of dielectric material from the baseof the contact is accomplished using apparatus known in the industry forsputter cleaning or plasma etching. Multi-chamber processing systems areavailable from industry sources such as Applied Materials Inc., of SantaClara, Calif.

[0048] III. The Contact Via Microstructure Which Reduces or PreventsJunction Spiking

[0049] Referring to FIG. 6, one embodiment of the semiconductor contactmicrostructure of the invention comprises a diffusion-barrier-linedfeature 8 comprising a silicon base 12 and a sidewall 5 which includes asilicon sidewall 14 adjacent the silicon base 12. The silicon sidewallextends less than 0.5 μm upward from the base of the feature. Theremainder 4 of the sidewall 5 of the feature 8 comprises a firstdielectric material 10. Overlying the silicon sidewall portion 14 is alayer 16 of a second dielectric material (which may or may not be thesame material as the first dielectric material 10). Overlying thesilicon base 6, the dielectric portion 4 of the sidewall 5, and at leasta portion of the silicon sidewall 14 is a diffusion barrier layer 22.

[0050] The second dielectric material is preferably selected from thegroup consisting of silicon oxide, silicon nitride, phosphorus siliconglass (PSG), and boron phosphorus silicon glass (BPSG); more preferably,silicon oxide; most preferably, thermally generated silicon oxide. Thethickness of the dielectric layer 16 overlying the silicon sidewallportion 14 is preferably within the range of about 50 Å to about 100 Å.

[0051] The diffusion barrier layer 22 preferably comprises a materialselected from the group consisting of titanium, titanium nitride,tantalum, tantalum nitride, and combinations thereof. The thickness ofthe diffusion barrier layer 22 is application-dependent and will varydepending upon the desired end use of the contact via microstructure.

[0052] IV. The Method of Forming the Contact Via Microstructure WhichReduces or Prevents Junction Spiking

[0053] The method of the invention for reducing or preventing junctionspiking due to silicon diffusion in an overetched contact via comprisesthe following general steps:

[0054] a) providing a semiconductor device feature which includes asilicon base, at least one silicon sidewall portion in contact with andextending upward from the silicon base, and at least one sidewallportion comprising a first dielectric material which is in contact withand extends upward from the silicon portion of the sidewall; and

[0055] b) creating a layer of a second dielectric material over the atleast one silicon sidewall portion.

[0056] Typically, the method also includes the steps:

[0057] c) sputter etching to remove dielectric material from the surfaceof the silicon base; and

[0058] d) applying a diffusion barrier material over the silicon base,the second dielectric layer overlying the silicon sidewall, and at leasta portion of the sidewall comprising a first dielectric material.

[0059] Referring to FIG. 4, the first step (a) of the method of thepresent invention involves providing a semiconductor device feature 8which includes a silicon base 12, at least one silicon sidewall 14extending upward from the silicon base less than about 0.5 μm, and atleast one sidewall 4 comprising a first dielectric material whichextends upward from the silicon sidewall 14. According to step (b), alayer 16 of a second dielectric material is formed on the bottom 6 andon the lower exposed silicon sidewalls 14 of the overetched contact via8. The dielectric layer 16 is preferably formed to have a thicknesswithin the range of about 50 Å to about 100 Å on the exposed siliconsidewalls 14.

[0060] The second dielectric material is preferably selected from thegroup including silicon oxide, silicon nitride, PSG, and BPSG, but maybe selected from other dielectric materials known to those skilled inthe art. The second dielectric material most preferably comprisessilicon oxide, which is typically formed by thermal oxidation. When thesecond dielectric material is formed by thermal oxidation, it will formonly on the exposed silicon surface, as shown in FIG. 4. Silicon oxidedeposited from TEOS using chemical vapor deposition (CVD) techniquesknown in the art is also acceptable. In addition, a PSG or BPSG or otherdielectric layer may be deposited on the interior surface of the contactvia using CVD techniques known in the art. When the second dielectricmaterial is formed by CVD deposition, it may extend not only over theexposed silicon surface, as shown in FIG. 4, but may also extend over aleast a portion of the first dielectric layer 10 (this extension overfirst dielectric layer 10 is not shown in FIG. 4). The advantage tousing CVD to deposit the second dielectric material is that thepossibility of diffusion of silicon from corner 13, as shown in FIG. 2,is reduced. The disadvantage is that the purity of the dielectricdeposited may not be as good.

[0061] Referring to FIG. 5, the third step (c) of the present inventioncomprises sputter etching to remove the dielectric material 16 from thebottom 6 of the contact via 8, but not from the sidewalls 14 of thecontact via 8. A sputter etch step (which may be called a “preclean”step) cleans the bottom 6 of the contact via 8 to expose bare silicon12. Preferably, the amount of material removed from the bottom 6 of thecontact via 8 is equal to approximately 1.5 times the thickness of thedielectric layer 16 which was deposited on the bottom of the contactvia. For example, if 100 Å of dielectric material were deposited on thebottom of the contact via, then roughly 150 Å of dielectric materialwould be removed from the bottom of the contact via by sputter etchingin order to ensure that all of the dielectric material had been removedfrom the bottom of the contact via. The sputter etch step is carried outunder anisotropic conditions, so that all of the dielectric material canbe removed from the bottom of the contact via, while minimal dielectricmaterial is removed from the sidewall.

[0062] A multi-chamber processing system having a separate sputter cleanchamber, such as the Applied Materials, Inc. (Santa Clara, Calif.)Endura® Integrated Processing System with Preclean™ II sputter cleanchamber, is preferably used.

[0063] Typical process conditions for the sputter etch step are asfollows: The argon flow rate into the process chamber is set at about 5sccm; and the RF plasma source power is set to be in the range of about400 kHz and at about 300 W. The power supply to the semiconductorsubstrate support platen, which was used to create a substrate bias, isset at about 13.56 MHZ and at about 300 W, to produce a bias on thesubstrate of about −250 V. The pressure in the process chamber was about0.5 mTorr to about 2.0 mTorr, the substrate temperature is about 300 °C. A typical sputter etch time is about 25 seconds.

[0064] Referring to FIG. 6, the final step (d) of the present inventioncomprises depositing a diffusion barrier layer 22 over the interiorsurface 2 of the contact via 8, including the bottom 6 of the contactvia 8, to reduce the possibility that silicon can diffuse at thejuncture between the sputtered bottom 6 of the contact via 8 and thedeposited sidewall dielectric 16. It is preferable to deposit thediffusion barrier layer 22 over the via interior surface so that thethickness of the diffusion barrier layer 22 at the bottom 6 of thecontact 8 is greater than 50% of the thickness of the dielectric layer16 sputtered off the bottom of the contact via during the preclean step.

[0065] If the contact via 8 is to be subsequently filled with aluminum,the diffusion barrier layer 22 is preferably titanium, titanium nitride,or a combination thereof. If the contact via 8 is to be filled withcopper, the diffusion barrier layer 22 is preferably tantalum, tantalumnitride, or a combination thereof. Other, less preferred barrier metalswhich may be used in the method of the invention include tungsten,zirconium, vanadium, chromium, molybdenum, niobium, or hafnium.

[0066] The diffusion barrier layer 22 is preferably deposited byphysical vapor deposition or chemical vapor metal deposition, mostpreferably, by high density plasma sputter deposition.

[0067] High density plasma sputter deposition of a titanium/titaniumnitride diffusion bi-layer is described, for example, in U.S. patentapplication Ser. No. 08/511,825, of Xu et al., assigned to the assigneeof the present invention, the disclosure of which is hereby incorporatedby reference herein in its entirety and summarized below. In general,the process for deposition of a titanium/titanium nitride diffusionbarrier layer comprises the steps of sputtering a titanium target,ionizing at least a portion of the titanium (10% to 100%) before it isdeposited on the substrate, attracting the ionized target materialtoward a biased substrate and forming a first sub-layer whichessentially performs a surface-wetting function, and then introducing asufficient quantity of nitrogen into the chamber as sputtering andionization continues, and reacting the nitrogen with the sputteredtitanium to form a film layer of titanium nitride (TiN) on thesubstrate. The flow of nitrogen gas to the chamber is typicallydiscontinued just prior to discontinuance of titanium target sputtering.

[0068] The specific process parameters for deposition of Ti/TiN barrierlayers will vary depending upon a variety of factors, including theparticular equipment used and the desired deposition rate of the Ti/TiNlayer. In an Applied Materials' ENDURA® process chamber, to obtain adeposition rate of titanium nitride/titanium layer of about 300 Å perminute upon the surface of an 8 inch (20.3 cm) diameter substrate, 1.5kW of RF power at 2 MHZ is applied to an internal coil, while 5 kW of DCpower is applied to the titanium target cathode, and an AC bias of 90 Wat 350 kHz is applied to the substrate platen electrode, resulting in aDC self-bias of about 70 V. The sputtering and ionization of thesputtered material is typically carried out in a process chamber withthe chamber pressure ranging from about 20 mTorr to about 30 mTorr. Toobtain the 300 Å per minute deposition rate, the sputtering andionization of the sputtered material is preferably carried out at about30 mTorr. This pressure corresponds to an argon feed rate of about 70sccm. The temperature of the substrate in the process chamber istypically about 50° C.

[0069] High density plasma sputter deposition of tantalum/tantalumnitride diffusion barrier layers is described, for example, in U.S.patent application Ser. No. 08/995,108, of Ding et al., assigned to theassignee of the present invention, the disclosure of which is herebyincorporated by reference herein in its entirety and summarized below.To form a TaN_(x)/Ta barrier layer structure, a tantalum target cathodeis used, and a DC power is applied to this cathode over a range fromabout 0.5 kW to about 8 kW. The spacing between the target cathode andthe workpiece is approximately 200-300 mm. During the formation of theTaN_(x) first layer, argon gas feed to the process chamber is about 15sccm to the substrate support platen and about 7 sccm to the openings inthe vicinity of the target cathode. Nitrogen gas is also fed into thevacuum chamber in the vicinity of the target cathode. The nitrogen gasfeed rate ranges from about 2 to about 20 sccm, depending on the DCpower applied, with the nitrogen feed rate being increased as the DCpower is increased. With the DC power set at 4 kW and a nitrogen feedrate of about 14 sccm, the TaN_(x) layer produced is TaN_(0.7),containing about 40 atomic percent nitrogen. The substrate is placed adistance of about 10 inches (25 cm) from the target cathode. Theoperational pressure in the vacuum chamber is about 1.7 mTorr, and thesubstrate temperature is about 25° C. Under these conditions, a 500 Åthick layer of TaN can be applied in approximately one minute.Subsequent to application of the TaN layer, the nitrogen gas is shutoff, the power to the tantalum target cathode is reduced from about 4 kWto about 1 kW, and the argon gas feed is maintained. The pressure in thevacuum chamber remains at about 1.7 mTorr, and the substrate temperatureremains at about 25° C. Under these conditions, a 60 Å thick layer oftantalum can be formed over the TaN layer in about 10 seconds.

[0070] Referring to FIG. 7, the method of the present inventionpreferably further includes the step (e) of applying a metallicconductor 24 over the diffusion barrier layer 22. Aluminum and copperare the preferred metallic conductors for use in the method of theinvention. Metallization of the contact with aluminum or copper ispreferably performed using high density plasma sputter deposition, butmay be applied by evaporation, electroplating, or chemical vapordeposition.

[0071] High density plasma sputter deposition of aluminum is described,for example, in U.S. patent application Ser. No. 08/511,825, of Xu etal., assigned to the assignee of the present invention, the disclosureof which is hereby incorporated by reference herein in its entirety andsummarized below. Initially, a layer of cold-sputtered aluminumapproximately 2,000 Å thick is applied over a barrier layer. Thiscold-sputtered aluminum layer, applied at a substrate temperature ofabout 150° C. or lower, provides a “seed” layer which adheres well to atitanium barrier layer. The bulk of the aluminum contact is thendeposited by sputtering at a temperature within the range of about 350°C. to about 450° C. The DC power is adjusted depending upon the desireddeposition rate. The sputtering is carried out in a process chamber overargon pressure ranging from about 0.5 mTorr to about 2 mTorr. Thiscorresponds to an argon feed rate of about 35 sccm in an AppliedMaterials 5500 Integrated Process System chamber.

[0072] High density plasma sputter deposition of copper is described,for example, in U.S. patent application Ser. No. 08/855,059, of Ding etal., assigned to the assignee of the present invention, the disclosureof which is hereby incorporated by reference herein in its entirety andsummarized below. In particular, the copper fill layer may be applied ina single-step process or in a two-step process. The selection of asingle-step process or a two-step process depends on the composition andstructure of the surface upon which the copper is being deposited andthe feature size of the trench or via to be filled. In the single-stepprocess, for feature sizes of about 0.75 μm or less, when the aspectratio of the feature to be filled is less than approximately 3:1, thetemperature of the substrate to which the copper fill layer is appliedshould range from about 200° C. to about 600° C. (preferably from about200° C. to about 500° C.); when the aspect ratio is about 3:1 orgreater, the copper fill layer should be applied over a temperatureranging from about 200° C. to about 600° C. (preferably from about 300°C. to about 500° C.). The deposition can be initiated at the low end ofthe temperature range, with the temperature being increased duringdeposition.

[0073] In the two-step process, a thin, continuous wetting (bonding)layer of copper is applied at a substrate surface temperature of about20° C. to about 250° C. The wetting layer thickness (on the wall of thetrench or via) should be a minimum of about 50 Å, and typically may beabout 100 Å to about 300 Å, depending on feature size and aspect ratio.Subsequently, the temperature of the substrate is increased, with theapplication of fill copper beginning at about 200° C. or higher andcontinuing as the temperature is increased to that appropriate for thefeature size. When both the copper wetting layer and the copper filllayer are applied in a single process chamber, the deposition may be acontinuous deposition. In such case, process conditions are variedduring the deposition, with the copper fill layer being applied at aslower rate than the copper wetting layer, to provide better depositioncontrol.

[0074] When the copper wetting layer is applied in one process chamberand the copper fill layer is applied in a second process chamber,typically the substrate with copper wetting layer already applied isplaced on a heated support platen in the second process chamber. For asmall feature size (0.5 μm or less) and an aspect ratio of 1:1 orgreater, it is better to wait until the substrate is heated to atemperature of at least 200° C. prior to beginning application of thecopper fill layer, or to begin the fill layer deposition at a slowerrate while the substrate is heating.

[0075] High density plasma sputter deposition of copper is carried outusing a copper target cathode having a 13.37 inch (33.96 cm) diameter,and DC power is applied to this cathode over a range from about 1 kW toabout 5 kW. The substrate is placed a distance of about 5.5 inches (14cm) from the copper target cathode. Typically, a substrate bias voltageranging from 0 to about −100 V DC is applied to the substrate byapplication of power to the platen under the substrate. The RF biaspower ranges from 0 W to about 500 W, and the frequency is typicallyfrom 350 kHz to 13.56 MHZ. In addition, a high density, inductivelycoupled RF plasma is generated in the region between the target cathodeand the substrate by applying RF power to a coil (having from 1 to 3turns) over a range from about 400 kHz to about 13.56 MHZ (preferablyabout 2 MHZ), at a wattage ranging from about 0.5 kW to about 5 kW(preferably about 1 kW to about 3 kW). The atmosphere in the processvessel is argon, the flow rate of the argon ranges from about 6 sccm toabout 140 sccm, and the process vessel pressure ranges from about 5mTorr to about 60 mTorr.

[0076] Referring again to FIG. 7, the method of the present inventiongreatly reduces or eliminates junction spiking at the bottom 6 of acontact via 8 when the via has been overetched, leaving exposed siliconsidewalls 14 adjacent the bottom 6 of the contact via 8. The presence ofthe dielectric layer 16 on the silicon sidewalls 14 of the contact via 8is effective to protect this portion of the sidewall from silicondiffusion and subsequent current leakage.

[0077] The above described preferred embodiments are not intended tolimit the scope of the present invention, as one skilled in the art can,in view of the present disclosure, expand such embodiments to correspondwith the subject matter of the invention claimed below.

We claim:
 1. A semiconductor contact microstructure which reducesjunction spiking, said microstructure comprising a feature whichincludes a silicon base, at least one silicon sidewall portion incontact with and extending upward from said silicon base, and at leastone sidewall portion comprising a first dielectric material which is incontact with said silicon sidewall portion, wherein, overlying at leastthe silicon portion of said sidewall is a layer of a second dielectricmaterial.
 2. The semiconductor contact microstructure of claim 1,further including a diffusion barrier layer overlying said silicon base,said second dielectric layer, and at least a portion of said firstdielectric sidewall material.
 3. The semiconductor contactmicrostructure of claim 1 or claim 2, wherein the height of said siliconsidewall portion extending upward from said silicon base is less thanabout 0.5 μm.
 4. The microstructure of claim 1 or claim 2, wherein saidsecond dielectric material is selected from the group consisting ofsilicon oxide, silicon nitride, PSG, and BPSG.
 5. The microstructure ofclaim 4, wherein said second dielectric material is silicon oxide. 6.The microstructure of claim 5, wherein said second dielectric materialis thermally generated silicon oxide.
 7. The microstructure of claim 1or claim 2, wherein the thickness of said layer of second dielectricmaterial overlying said silicon portion of said sidewall is within therange of about 50 Å to about 100 Å.
 8. The microstructure of claim 2,wherein said diffusion barrier layer comprises a material selected fromthe group consisting of titanium, titanium nitride, tantalum, tantalumnitride, and combinations thereof.
 9. A method of reducing or preventingjunction spiking in a contact via formed in a silicon substrate, themethod comprising the following steps: a) providing a semiconductordevice feature which includes a silicon base and at least one sidewallextending upward from said silicon base, where said sidewall includes atleast one silicon portion in contact with said silicon base and anotherportion comprising a first dielectric material which is in contact withsaid silicon portion of said sidewall; and b) creating a layer of asecond dielectric material over said at least one silicon portion ofsaid sidewall.
 10. The method of claim 9, including the additionalsteps: c) sputter etching to remove dielectric material from a surfaceof said silicon base; and d) applying a diffusion barrier layer oversaid silicon base, said second dielectric layer overlying said siliconportion of said sidewall, and at least a portion of said sidewallcomprising a first dielectric material.
 11. The method of claim 9 orclaim 10, wherein the height of said silicon sidewall portion extendingupward from said silicon base is less than about 0.5 μm.
 12. The methodof claim 11, wherein said second dielectric material is selected fromthe group consisting of silicon oxide, silicon nitride, PSG, and BPSG.13. The method of claim 12, wherein said second dielectric material issilicon oxide.
 14. The method of claim 13, wherein said silicon oxide isformed by thermal oxidation.
 15. The method of claim 12, wherein saidlayer of second dielectric material is deposited using chemical vapordeposition.
 16. The method of claim 9 or claim 10, wherein said layer ofsecond dielectric material is formed to have a thickness within therange of about 50 Å to about 100 Å.
 17. The method of claim 10, whereinsaid diffusion barrier layer comprises a material selected from thegroup consisting of titanium, titanium nitride, tantalum, tantalumnitride, and combinations thereof.
 18. The method of claim 17, whereinsaid diffusion barrier layer is deposited by physical vapor deposition.19. The method of claim 18, wherein said diffusion barrier layer isdeposited by high density plasma sputter deposition.
 20. The method ofclaim 10, wherein the method further comprises the following step: e)applying a metallic conductor over said diffusion barrier layer.
 21. Themethod of claim 20, wherein said metallic conductor is aluminum, andsaid diffusion barrier layer comprises a material selected from thegroup consisting of titanium, titanium nitride, and combinationsthereof.
 22. The method of claim 20, wherein said metallic conductor iscopper, and said diffusion barrier layer comprises a material selectedfrom the group consisting of tantalum, tantalum nitride, andcombinations thereof.